Inter-integrated circuit (I
2
C) interface RM0008
582/690
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection may be enabled or disabled
by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to the following figure.
Figure 230. I
2
C bus protocol
Acknowledge may be enabled or disabled by software. The I
2
C interface addresses (dual
addressing 7-bit/ 10-bit and/or general call address) can be selected by software.
The block diagram of the I
2
C interface is shown in Figure 231.
SCL
SDA
12 89
MSB
ACK
Stop
Start
condition
condition
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