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Memory and bus architecture RM0008

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DCode bus

This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core

to the Flash memory Data interface.

System bus

This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix

which manages the arbitration between the core and the DMA.

DMA bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages

the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.

BusMatrix

The BusMatrix manages the access arbitration between the core system bus and the DMA

master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of

three masters (CPU DCode, System bus and DMA bus) and three slaves (FLITF, SRAM,

and AHB2APB bridges).

AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB/APB bridges (APB)

The two AHB/APB bridges provide full synchronous connections between the AHB and the

2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz

depending on the device).

Refer to Table 1 on page 36 for the address mapping of the peripherals connected to each

bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).

Before using a peripheral you have to enable its clock in the RCC_AHBENR,

RCC_APB2ENR or RCC_APB1ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into

a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

Program memory, data memory, registers and I/O ports are organized within the same linear

4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word

is considered the word’s least significant byte and the highest numbered byte the most

significant.

Figure 2 on page 35 shows the STM32F10xxx memory map. For the detailed mapping of

peripheral registers, please refer to the related chapters.

The addressable memory space is divided into 8 main blocks, each of 512 MB.

All the memory areas that are not allocated to on-chip memories and peripherals are

considered “Reserved” (gray shaded areas in the Figure 2 on page 35).

ST STM32F102 series User Manual

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