General-purpose timer (TIMx) RM0008
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13.4.3 Slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
Bits 6:4 MMS: Master Mode Selection.
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is
generated by the trigger input (slave mode controller configured in reset mode) then the signal on
TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to
start several timers at the same time or to control a window in which a slave timer is enabled. The
Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input
when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except
if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master timer
can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set
(even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
110: Compare - OC3REF signal is used as trigger output (TRGO).
111: Compare - OC4REF signal is used as trigger output (TRGO).
Bit 3 CCDS: Capture/Compare DMA Selection.
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, always read as 0
1514131211109876543210
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0]
Res.
SMS[2:0]
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