RM0008 Debug support (DBG)
675/690
Note: By default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK
two clock cycles after the bit TRACE_IOEN has been set.
The debugger must then program the Trace Mode by writing the PROTOCOL[1:0] bits in the
SPP_R (Selected Pin Protocol) register of the TPIU.
● PROTOCOL=00: Trace Port Mode (synchronous)
● PROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode).
Default state is 01
It then also configures the TRACE port size by writing the bits [3:0] in the CPSPS_R
(Current Sync Port Size Register) of the TPIU:
● 0x1 for 1 pin (default state)
● 0x2 for 2 pins
● 0x8 for 4 pins
26.16.3 TPUI formatter
The formatter protocol outputs data in 16-byte frames:
● seven bytes of data
● eight bytes of mixed-use bytes consisting of:
– 1 bit (LSB) to indicate it is a DATA byte (‘0’) or an ID byte (‘1’).
– 7 bits (MSB) which can be data or change of source ID trace.
● one byte of auxiliary bits where each bit corresponds to one of the eight mixed-use
bytes:
– if the corresponding byte was a data, this bit gives bit0 of the data.
– if the corresponding byte was an ID change, this bit indicates when that ID change
takes effect.
Note: Refer to the ARM CoreSight Architecture Specification v1.0 (ARM IHI 0029B) for further
information
Use of the formatter for STM32F10xxx MCU
101
Synchronous Trace
1 bit
Released
(1)
TRACE
CK
TRACE
D[0]
110
Synchronous Trace
2 bit
TRACE
CK
TRACE
D[0]
TRACE
D[1]
111
Synchronous Trace
4 bit
TRACE
CK
TRACE
D[0]
TRACE
D[1]
TRACE
D[2]
TRACE
D[3]
(1)
When Serial Wire mode is used, it is released. But when JTAG is used, it is assigned to JTDO.
Table 171. Flexible TRACE pin assignment (continued)
DBGMCU_CR
register
Pins assigned for:
TRACE I/O pin assigned
TRACE_
IOEN
TRACE_
MODE[1:0]
PB3 /
JTDO/
TRACES
WO
PE2 /
TRACE
CK
PE3 /
TRACE
D[0]
PE4 /
TRACE
D[1]
PE5 /
TRACE
D[2]
PE6 /
TRACE
D[3]
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