Serial peripheral interface (SPI) RM0008
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To ensure a continuous audio data transmission, it is mandatory to write the SPI_DR with
the next data to transmit before the end of the current transmission.
To switch off the I
2
S, by clearing I2SE, it is mandatory to wait for TXE = 0 and BSY = 0.
Reception sequence
The operating mode is the same as for the transmission mode except for the point 3, where
the configuration should set the master reception mode through the I2SCFG[1:0] bits.
Whatever the data or channel length, the audio data are received by 16-bit packets. This
means that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated
if the RXNEIE bit is set in SPI_CR2 register. Depending on the data and channel length
configuration, the audio value received for a right or left channel may result from one or two
receptions into the Rx buffer.
Clearing the RXNE bit is performed by reading the SPI_DR register.
CHSIDE is updated after each reception. It is sensitive to the WS signal generated by the
I
2
S cell.
For more details about the read operations depending on the I
2
S standard mode selected,
refer to Section 22.4.2: Supported audio protocols.
If data are received while the precedent received data have not been read yet, an overrun is
generated and the OVR flag is set. If the ERRIE bit is set in the SPI_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I
2
S in reception mode, I2SE has to be cleared during and before the end of
the last data reception. Even if I2SE is switched off while the last data are being transferred,
the clock and the transfer are maintained until the end of the current data transmission.
22.4.5 I
2
S slave mode
For the slave configuration, the I
2
S can be configured in transmission or reception mode.
The operating mode is following mainly the same rules as described for the I
2
S master
configuration. In slave mode, there is no clock to be generated by the I
2
S interface. The
clock and WS signals are input from the external master connected to the I
2
S interface.
There is then no need, for the user, to configure the clock.
The configuration steps to follow are listed below:
1. Set the I2SMOD bit in the SPI_I2SCFGR register to reach the I
2
S functionalities and
choose the I
2
S standard through the I2SSTD[1:0] bits, the data length through the
DATLEN[1:0] bits and the number of bits per channel for the frame configuring the
CHLEN bit. Select also the mode (transmission or reception) for the slave through the
I2SCFG[1:0] bits in SPI_I2SCFGR register.
2. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPI_CR2 register.
3. The I2SE bit in SPI_I2SCFGR register must be set.
Transmission sequence
The transmission sequence begins when a half-word (corresponding to channel Left data) is
written to the Tx buffer. When data are transferred from the Tx buffer to the shift register, the
TXE flag is set and data corresponding to the channel Right have to be written into the Tx
buffer. The CHSIDE flag indicates which channel is to be transmitted. Compared to the
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