ST STM32F102 series - Table 83. Fsmc_Bcrx Bit Fields; Table 84. Fsmc_Tcrx Bit Fields; Table 85. Fsmc_Bwtrx Bit Fields

RM0008 Flexible static memory controller (FSMC)
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Table 83. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-15 0x0000
14 EXTMOD 1
13-10 0x0
9 WAITPOL Meaningful only if bit 15 is 1.
8 BURSTEN 0
7 -
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP 10 (NOR Flash).
1 MUXEN 0
0 MBKEN 1
Table 84. FSMC_TCRx bit fields
Bit No. Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x2
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) in
read. This value cannot be 0 (minimum is 1)
7-4 0x0
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) in
read.
Table 85. FSMC_BWTRx bit fields
Bit No. Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x2
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles) in
write. This value cannot be 0 (minimum is 1)
7-4 0x0
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) in
write.