ST STM32F102 series

Flexible static memory controller (FSMC) RM0008
378/690
Table 78. FSMC_TCRx bit fields
Bit
number
Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x0
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) in
read. This value cannot be 0 (minimum is 1)
7-4 0x0
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read.
Table 79. FSMC_BWTRx bit fields
Bit
number
Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x0
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles) in
write. This value cannot be 0 (minimum is 1)
7-4 0x0
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in write.