Revision history RM0008
682/690
20-Nov-2007 2
Figure 237: USART block diagram modified.
Procedure modified in Character reception on page 618.
In Section 24.3.4: Fractional baud rate generation:
– Equation legend modified
– Table 153: Error calculation for programmed baud rates modified
– Note added
Small text changes. In CAN bit timing register (CAN_BTR) on page 527, bit
15 is reserved.
Flash memory organization corrected, Table 3: Flash module organization
(medium-density devices) modified in Section 2.3.4: Embedded Flash
memory.
Note added below Figure 4: Power supply overview in Section 4.1: Power
supplies.
RTCSEL[1:0] bit description modified in Backup domain control register
(RCC_BDCR).
Names of bits [0:2] corrected for RCC_APB1RSTR and RCC_APB1ENR in
Table 14: RCC - register map and reset values.
Impedance value specified in A.4: Voltage glitch on ADC input 0 on
page 500.
In Section 22.5.1: SPI Control Register 1 (SPI_CR1) (not used in I
2
S mode),
BR[2:0] description corrected.
Prescaler buffer behavior specified when an update event occurs (see
upcounting mode on page 277, Downcounting mode on page 280 and
Center-aligned mode (up/down counting) on page 282).
AWDCH[4:0] modified in Section 10.12.2: ADC control register 1
(ADC_CR1) and bits [26:24] are reserved in Section 10.12.4: ADC sample
time register 1 (ADC_SMPR1).
CAN_BTR bit 8 is reserved in Table 145: bxCAN - register map and reset
values. CAN master control register (CAN_MCR) on page 518 corrected.
V
REF+
range corrected in Table 42: ADC pins and in On 100-pin and 144- pin
packages on page 49.
Start condition on page 586 updated. Note removed in Table 17: BXCAN
alternate function remapping. Note added in Table 25: Timer 4 alternate
function remapping.
In Section 7.4.2: AF remap and debug I/O configuration register
(AFIO_MAPR), bit definition modified for USART2_REMAP = 0. In
Section 7.4.3: External interrupt configuration register 1 (AFIO_EXTICR1),
bit definition modified for SPI1_REMAP = 0.
In Table 172: Important TPIU registers, at 0xE0040004, bit2 set is not
supported.
TRACE port size setting corrected in TPUI TRACE pin assignment on
page 674. Figure 10, Figure 12, Figure 13, Figure 14 and Figure 15
modified. Figure 11: Basic structure of a five-volt tolerant I/O port bit added.
Table 7.3.1: Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
on page 110 added.
Bit descriptions modified in Section 15.4.5 and Section 15.4.6.
JTAG ID code corrected in Section 26.6.2: Boundary scan TAP on page 660
.
Modified: Section 17.2: WWDG main features, Section 5.2: BKP main
features, Section 5.3.1: Tamper detection, Section 5.3.2: RTC calibration,
Section 20.3: USB functional description, Controlling the downcounter: on
page 361, Section 4.1.2: Battery backup domain, Section 8.2: Introduction.
ASOE bit description modified in Section 5.4.2: RTC clock calibration
register (BKP_RTCCR).
Table 174. Document revision history (continued)
Date Revision Changes
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