ST STM32F102 series

RM0008 Advanced-control timers (TIM1&TIM8)
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12.4 TIM1&TIM8 registers
Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions.
12.4.1 Control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
1514131211109876543210
Reserved CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
Res. rw rw rw rw rw rw rw rw rw rw
Bits 15:10 Reserved, always read as 0
Bits 9:8 CKD[1:0]: Clock division.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-
time and sampling clock (t
DTS
)used by the dead-time generators and the digital filters (ETR, TIx),
00: t
DTS
=t
CK_INT
01: t
DTS
=2*t
CK_INT
10: t
DTS
=4*t
CK_INT
11: Reserved, do not program this value.
Bit 7 ARPE: Auto-reload preload enable.
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:5 CMS[1:0]: Center-aligned mode selection.
00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt
flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the
counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt
flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the
counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt
flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the
counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the
counter is enabled (CEN=1)
Bit 4 DIR: Direction.
0: Counter used as upcounter.
1: Counter used as downcounter.
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
Bit 3 OPM: One pulse mode.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN).