RM0008 General-purpose timer (TIMx)
309/690
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.
Figure 140. Triggering timer 1 and 2 with timer 1 TI1 input.
13.3.16 Debug mode
When the microcontroller enters debug mode (Cortex-M3 core - halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 26.15.2: Debug support for timers,
watchdog, bxCAN and I2C.
00 01
CK_INT
TIMER1-CEN=CNT_EN
TIMER1-CNT
TIMER 1-TI1
TIMER 1-CK_PSC
02 03 04 05 06 07 08 09
TIMER1-TIF
00 01
TIMER2-CEN=CNT_EN
TIMER2-CNT
TIMER 2-CK_PSC
02 03 04 05 06 07 08 09
TIMER2-TIF
To Next Page
Loading...
Need help?
General
