Reset and clock control (RCC) RM0008
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configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock
of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
FCLK acts as Cortex™-M3 free running clock. For more details refer to the ARM Cortex™-
M3 Technical Reference Manual.
6.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
● HSE external crystal/ceramic resonator
● HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 9. HSE/ LSE clock sources
Hardware configuration
External ClockCrystal/Ceramic Resonators
OSC_OUT
EXTERNAL
SOURCE
(HiZ)
OSC_IN OSC_OUT
LOAD
CAPACITORS
C
L2
C
L1
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