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RM0008 Backup registers (BKP)

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5.4.4 Backup control/status register (BKP_CSR)

Address offset: 0x34

Reset value: 0x0000 0000

14 13 12 11 10 9 8 7 6 5 4 3 2 1

Reserved TIF TEF Reserved TPIE CTI CTE

Res. r r Res. rw w w

Bits 15:10 Reserved, always read as 0.

Bit 9 TIF Tamper Interrupt Flag

This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by

writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is reset.

0: No Tamper interrupt

1: A Tamper interrupt occurred

Note: This bit is reset only by a system reset and wakeup from Standby mode.

Bit 8 TEF Tamper Event Flag

This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the CTE bit.

0: No Tamper event

1: A Tamper event occurred

Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the TEF bit

is set. If a write to the BKP_DRx registers is performed while this bit is set, the value will not be stored.

Bits 7:3 Reserved, always read as 0.

Bit 2 TPIE TAMPER Pin interrupt enable

0: Tamper interrupt disabled

1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register

Note 1: A Tamper interrupt does not wake up the core from low-power modes.

Note 2: This bit is reset only by a system reset and wakeup from Standby mode.

Bit 1 CTI Clear Tamper Interrupt

This bit is write only, and is always read as 0.

0: No effect

1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.

Bit 0 CTE Clear Tamper event

This bit is write only, and is always read as 0.

0: No effect

1: Reset the TEF Tamper event flag (and the Tamper detector)

ST STM32F102 series User Manual

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