RM0008 SDIO interface (SDIO)
457/690
19.9.7 SDIO Data Timer Register (SDIO_DTIMER)
Address offset: 0x24
Reset value: 0x0000 0000
The SDIO_DTIMER register contains the data timeout period, in card bus clock periods.
A counter loads the value from the SDIO_DTIMER register, and starts decrementing when
the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0
while the DPSM is in either of these states, the timeout status flag is set.
Note: A data transfer must be written to the data timer register and the data length register before
being written to the data control register.
19.9.8 SDIO Data Length Register (SDIO_DLEN)
Address offset: 0x28
Reset value: 0x0000 0000
The SDIO_DLEN register contains the number of data bytes to be transferred. The value is
loaded into the data counter when data transfer starts.
Note: For a block data transfer, the value in the data length register must be a multiple of the block
size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the
data length register before being written to the data control register.
313029282726252423222120191817161514131211109876543210
DATATIME
r/w
Bits 31:0 DATATIME: Data timeout period.
Data timeout period expressed in card bus clock periods.
313029282726252423222120191817161514131211109876543210
Reserved DATALENGTH
Res. r/w
Bits 31:25 Reserved, always read as 0.
Bits 24:0 DATALENGTH: Data length value.
Number of data bytes to be transferred.
To Next Page
Loading...
Need help?
General
