RM0008 Revision history
681/690
19-Oct-2007
continued
1
continued
Figure 109: Counter timing diagram, internal clock divided by 1,
TIMx_ARR=0x6 and Figure 124: Output compare mode, toggle on OC1.
modified.
CKD definition modified in Section 13.4.1: Control register 1 (TIMx_CR1).
Bit 8 and Bit 9 added to Section 5.4.2: RTC clock calibration register
(BKP_RTCCR).
Bit 15 and Bit 16 added to DBGMCU_CR on page 671. Section 23.5: I
2
C
debug mode on page 596 added.
Stop and Standby modified in Table 7: Low-power mode summary.
Table 9: Sleep-on-exit modified. Debug mode on page 56 modified.
HSITRIM[4:0] bit description modified in Section 6.3.1: Clock control register
(RCC_CR). Note modified in MCO description in Section 6.3.2: Clock
configuration register (RCC_CFGR). RCC_CR row modified in RCC -
register map and reset values on page 96.
Bits 15:0 description modified in Section 7.2.6: Port bit reset register
(GPIOx_BRR) (x=A..G). Embedded boot loader on page 43 added.
Figure 10, Figure 12, Figure 13, Figure 14 and Figure 15 modified.
Section 2.3.4: Embedded Flash memory on page 39 modified.
REV_ID bit description added to DBGMCU_IDCODE on page 659.
Reset value modified in Clock control register (RCC_CR) on page 77 and
HSITRIM[4:0] description modified.
Section 7.1.1 on page 99 modified. Bit definitions modified in Section 7.2:
GPIO registers on page 105. Wakeup latency description modified in
Table 10: Stop mode.
Clock control register (RCC_CR) reset value modified.
Note added in ASOS and ASOE bit descriptions in 5.4.2 on page 63.
Section 26.15.2: Debug support for timers, watchdog, bxCAN and I2C
modified. Table 173: DBG - register map and reset values updated.
Section 20.5.3: Buffer descriptor table clarified.
Center-aligned mode (up/down counting) on page 215 and Center-aligned
mode (up/down counting) on page 282 updated.
Figure 80: Center-aligned PWM waveforms (ARR=8) on page 230 and
Figure 126: Center-aligned PWM waveforms (ARR=8) on page 295
modified.
RSTCAL description modified in Section 10.12.3: ADC control register 2
(ADC_CR2).
Note changed below Table 63: Watchdog timeout period (with 40 kHz input
clock). Note added below Figure 8: Clock tree.
ADC conversion time modified in Section 10.2: ADC main features.
Auto-injection on page 154 updated.
Note added in Section 10.9.9: Combined injected simultaneous +
interleaved. Note added to Section 7.3.2: Using OSC_IN/OSC_OUT pins as
GPIO ports PD0/PD1. Small text changes. Internal LSI RC frequency
changed from 32 to 40 kHz. Table 63: Watchdog timeout period (with 40 kHz
input clock)
updated. Option byte addresses corrected in Figure 2: Memory
map and Table 3: Flash module organization (medium-density devices).
Information block organization modified in Section 2.3.4: Embedded Flash
memory.
External event that trigger ADC conversion is EXTI line instead of external
interrupt (see Section 10: Analog-to-digital converter (ADC)).
Appendix A: Important notes on page 500 added.
Table 174. Document revision history (continued)
Date Revision Changes
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