Advanced-control timers (TIM1&TIM8) RM0008
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12.4.3 Slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
1514131211109876543210
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] Res. SMS[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw Res. rw rw rw
Bit 15 ETP: External trigger polarity.
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable.
This bit enables External clock mode 2.
0: External clock mode 2 disabled.
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Note 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
Note 2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this
case (TS bits must not be 111).
Note 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external
clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler.
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can
be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler OFF.
01: ETRP frequency divided by 2.
10: ETRP frequency divided by 4.
11: ETRP frequency divided by 8.
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