Revision history RM0008
684/690
22-May-2008
continued
4
continued
In Section 6: Reset and clock control (RCC) on page 69:
– LSI calibration on page 74 added
– Figure 7: Reset circuit on page 70 updated
– APB2 peripheral reset register (RCC_APB2RSTR) on page 83 updated
– APB1 peripheral reset register (RCC_APB1RSTR) on page 85 updated
– AHB Peripheral Clock enable register (RCC_AHBENR) updated
– APB2 peripheral clock enable register (RCC_APB2ENR) updated
– APB1 peripheral clock enable register (RCC_APB1ENR) on page 90
updated (see Section Table 14.: RCC - register map and reset values).
– LSERDYIE definition modified in Clock interrupt register (RCC_CIR)
– HSITRIM[4:0] definition modified in Clock control register (RCC_CR)
In Section 7: General-purpose and alternate-function I/Os (GPIOs and
AFIOs) on page 97:
– GPIO ports F and G added
–In Section 7.3: Alternate function I/O and debug configuration (AFIO) on
page 110 remapping for High-density devices added, note modified under
Section 7.3.2, Section 7.3.3 on page 110 modified
– AF remap and debug I/O configuration register (AFIO_MAPR) on
page 117 updated
Updated in Section 8: Interrupts and events on page 123:
– number of maskable interrupt channels
– number of GPIOs (see Figure 17: External interrupt/event GPIO mapping)
In Section 9: DMA controller (DMA) on page 134:
– number of DMA controllers and configurable DMA channels updated
– Figure 18: DMA block diagram on page 135 updated, notes added
– Note updated in Section 9.3.2: Arbiter on page 136
– Note updated in Section 9.3.5: Interrupts on page 138
– Figure 19: DMA1 request mapping on page 139 updated
– DMA2 controller on page 140 added
In Section 10: Analog-to-digital converter (ADC) on page 149:
– ADC3 added (Figure 21: Single ADC block diagram on page 150 updated,
Table 47: External trigger for injected channels for ADC3 on page 159
added, etc.)
Section 11: Digital-to-analog converter (DAC) on page 184 added.
In Section 12: Advanced-control timers (TIM1&TIM8) on page 206:
– Advanced control timer TIM8 added (see Figure 47: Advanced-control
timer block diagram on page 208)
– TS[2:0] modified in Section 12.4.3: Slave mode control register
(TIMx_SMCR) on page 250
.
In Section 13: General-purpose timer (TIMx) on page 273:
– TIM5 added
– Figure 95: General-purpose timer block diagram on page 275 updated.
Table 58: TIMx Internal trigger connection on page 314 modified.
Section 14: Basic timer (TIM6&7) on page 330 added.
RTC clock sources specified in Section 15.2: RTC main features on
page 343. Section 15.1: RTC introduction modified.
Section 18: Flexible static memory controller (FSMC) on page 365 added.
Section 19: SDIO interface (SDIO) on page 412 added.
Table 174. Document revision history (continued)
Date Revision Changes
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