Advanced-control timers (TIM1&TIM8) RM0008
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12.4.2 Control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
Bit 2 URS: Update request source.
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled. These events
can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bit 1 UDIS: Update disable.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC,
CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware
reset is received from the slave mode controller.
Bit 0 CEN: Counter enable.
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously
set by software. However trigger mode can set the CEN bit automatically by hardware.
1514131211109876543210
Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC
Res. rw rw rw rw rw rw rw rw rw rw rw rw rw Res. rw
Bit 15 Reserved, always read as 0
Bit 14 OIS4: Output Idle state 4 (OC4 output).
refer to OIS1 bit
Bit 13 OIS3N: Output Idle state 3 (OC3N output).
refer to OIS1N bit
Bit 12 OIS3: Output Idle state 3 (OC3 output).
refer to OIS1 bit
Bit 11 OIS2N: Output Idle state 2 (OC2N output).
refer to OIS1N bit
Bit 10 OIS2: Output Idle state 2 (OC2 output).
refer to OIS1 bit
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