Basic timer (TIM6&7) RM0008
336/690
Figure 150. Control circuit in normal mode, internal clock divided by 1
14.3.4 Debug mode
When the microcontroller enters the debug mode (Cortex-M3 core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to Section 26.15.2: Debug
support for timers, watchdog, bxCAN and I2C.
14.4 TIM6&TIM7 registers
Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions.
14.4.1 Control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
CK_INT
00
Counter clock = CK_CNT = CK_PSC
COUNTER REGISTER
01 02 03 04 05 06 0732 33 34 35 3631
CEN=CNT_EN
UG
CNT_INIT
1514131211109876543210
Reserved ARPE Reserved OPM URS UDIS CEN
Res. rw Res. rw rw rw rw
Bits 15:8 Reserved, always read as 0
Bit 7 ARPE: Auto-Reload Preload enable.
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, always read as 0
Bit 3 OPM: One-Pulse Mode.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
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