ST STM32F102 series

Inter-integrated circuit (I
2
C) interface RM0008
606/690
23.6.8 Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note: 1 F
PCLK1
is the multiple of 10 MHz required to generate the Fast clock at 400 kHz.
2 The CCR register must be configured only when the I2C is disabled (PE = 0).
Bit 2 TRA: Transmitter/Receiver
0: Data bytes received
1: Data bytes transmitted
This bit is set depending on R/W bit of address byte, at the end of total address phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition,
loss of bus arbitration (ARLO=1), or when PE=0.
Bit 1 BUSY: Bus Busy
0: No communication on the bus
1: Communication ongoing on the bus
– Set by hardware on detection of SDA or SCL low
– cleared by hardware on detection of a Stop condition.
It indicates a communication in progress on the bus. This information is still updated when the
interface is disabled (PE=0).
Bit 0 MSL: Master/Slave
0: Slave Mode
1: Master Mode
– Set by hardware as soon as the interface is in Master mode (SB=1).
– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1), or
by hardware when PE=0.
151413121110987 654321 0
F/S DUTY
Reserved
CCR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 F/S I
2
C Master Mode Selection
0: Standard Mode I2C
1: Fast Mode I2C