ST STM32F102 series User Manual

DMA controller (DMA) RM0008
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9.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7)
Address offset: 0x10 + dx20 × Channel number
Reset value: 0x0000 0000
9.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7)
Address offset: 0x14 + dx20 × Channel number
Reset value: 0x0000 0000
9.4.7 DMA register map
The following table gives the DMA register map and the reset values.
Bits 31:0 PA[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
Bits 31:0 MA[31:0]: Memory Address
Base address of the memory area from/to which the data will be read/written.
Table 41. DMA - register map and reset values
Offset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
0x000
DMA_ISR
Reserved
TEIF7
HTIF7 TCIF7
GIF7
TEIF6
HTIF6 TCIF6
GIF6
TEIF5
HTIF5 TCIF5
GIF5
TEIF4
HTIF4 TCIF4
GIF4
TEIF3
HTIF3 TCIF3
GIF3
TEIF2
HTIF2 TCIF2
GIF2
TEIF1
HTIF1 TCIF1
GIF1
Reset value 0000000000000000000000000000
0x004
DMA_IFCR
Reserved
CTEIF7
CHTIF7 CTCIF7
CGIF7
CTEIF6
CHTIF6 CTCIF6
CGIF6
CTEIF5
CHTIF5 CTCIF5
CGIF5
CTEIF4
CHTIF4 CTCIF4
CGIF4
CTEIF3
CHTIF3 CTCIF3
CGIF3
CTEIF2
CHTIF2 CTCIF2
CGIF2
CTEIF1
CHTIF1 CTCIF1
CGIF1
Reset value 0000000000000000000000000000
0x008
DMA_CCR1
Reserved
MEM2MEM
PL
[1:0]
M
SIZE
[1:0]
PSIZE
[1:0]
MINC
PINC
CIRC
DIR
TEIE
HTIE TCIE
EN
Reset value 000000000000000
0x00C
DMA_CNDTR1
Reserved
NDT[15:0]
Reset value 0000000000000000
0x010
DMA_CPAR1 PA[31:0]
Reset value 00000000000000000000000000000000
0x014
DMA_CMAR1 MA[31:0]
Reset value 00000000000000000000000000000000
0x018 Reserved
0x01C
DMA_CCR2
Reserved
MEM2MEM
PL
[1:0]
M
SIZE
[1:0]
PSIZE
[1:0]
MINC
PINC
CIRC
DIR
TEIE
HTIE TCIE
EN
Reset value 000000000000000
0x020
DMA_CNDTR2
Reserved
NDT[15:0]
Reset value 0000000000000000

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English