RM0008 General-purpose timer (TIMx)
323/690
Input capture mode
13.4.9 Capture/compare enable register (TIMx_CCER)
Address offset: 0x20
Reset value: 0x0000
Bits 15:12 IC4F: Input Capture 4 Filter.
Bits 11:10 IC4PSC: Input Capture 4 Prescaler.
Bits 9:8 CC4S: Capture/Compare 4 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output.
01: CC4 channel is configured as input, IC4 is mapped on TI4.
10: CC4 channel is configured as input, IC4 is mapped on TI3.
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in TIMx_CCER).
Bits 7:4 IC3F: Input Capture 3 Filter.
Bits 3:2 IC3PSC: Input Capture 3 Prescaler.
Bits 1:0 CC3S: Capture/Compare 3 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output.
01: CC3 channel is configured as input, IC3 is mapped on TI3.
10: CC3 channel is configured as input, IC3 is mapped on TI4.
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in TIMx_CCER).
1514131211109876543210
Reserved
CC4P CC4E
Reserved
CC3P CC3E
Reserved
CC2P CC2E
Reserved
CC1P CC1E
rw rw rw rw rw rw rw rw
Bits 15:14 Reserved, always read as 0.
Bit 13 CC4P: Capture/Compare 4 output Polarity.
refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable.
refer to CC1E description
Bits 11:10 Reserved, always read as 0.
Bit 9 CC3P: Capture/Compare 3 output Polarity.
refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable.
refer to CC1E description
Bits 7:6 Reserved, always read as 0.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
refer to CC1P description
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