ST STM32F102 series

Flexible static memory controller (FSMC) RM0008
372/690
NOR Flash, multiplexed I/Os
NOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit
(26 address lines).
PSRAM
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
Table 72. Muxed I/O NOR Flash
FSMC signal name I/O Function
CLK O Clock (for synchronous burst)
A[25:16] O Address bus
AD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus
NE[x] O Chip select, x = 1..4
NOE O Output enable
NWE O Write enable
NL(=NADV) O
Latch enable (this signal is called address valid, NADV, by some NOR
Flash devices)
NWAIT I NOR Flash wait input signal to the FSMC
Table 73. PSRAM
FSMC signal name I/O Function
CLK O Clock (for synchronous burst)
A[25:0] O Address bus
D[15:0] I/O Data bidirectional bus
NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FSMC
NBL[1] O Upper byte enable (memory signal name: NUB)
NBL[0] O Lowed byte enable (memory signal name: NLB)