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ST STM32F102 series User Manual

ST STM32F102 series
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Window watchdog (WWDG) RM0008
362/690
17.4 How to program the watchdog timeout
Figure 156 shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 156.
Warning: When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 156. Window watchdog timing diagram
T6 bit
Reset
W[6:0]
T[6:0] CNT downcounter
time
Refresh WindowRefresh not allowed
3Fh
The formula to calculate the timeout value is given by:
where:
T
WWDG
: WWDG timeout
T
PCLK1
: APB1 Clock period measured in ms
Min-max timeout value @36MHz (PCLK1)
WDGTB Min timeout value Max timeout value
0 113 µs 7.28 ms
1 227 µs 14.56 ms
2 455 µs 29.12 ms
3 910 µs 58.25 ms
T
WWDG
T
PCLK1
4096× 2
WDGTB
× T5:0[]1+()×= ms();

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ST STM32F102 series Specifications

General IconGeneral
BrandST
ModelSTM32F102 series
CategoryMicrocontrollers
LanguageEnglish

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