Inter-integrated circuit (I
2
C) interface RM0008
580/690
23 Inter-integrated circuit (I
2
C) interface
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
23.1 Introduction
I
2
C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller
and the serial I
2
C bus. It provides multimaster capability, and controls all I
2
C bus-specific
sequencing, protocol, arbitration and timing. It supports standard and fast speed modes. It is
also SMBus 2.0 compatible.
It may be used for a variety of purposes, including CRC generation and verification, SMBus
(system management bus) and PMBus (power management bus).
Depending on specific device implementation DMA capability can be available for reduced
CPU overload.
23.2 I
2
C main features
● Parallel-bus/I
2
C protocol converter
● Multimaster capability: the same interface can act as Master or Slave
● I
2
C Master features:
– Clock generation
– Start and Stop generation
● I
2
C Slave features:
– Programmable I
2
C Address detection
– Dual Addressing Capability to acknowledge 2 slave addresses
– Stop bit detection
● Generation and detection of 7-bit/10-bit addressing and General Call
● Supports different communication speeds:
– Standard Speed (up to 100 kHz),
– Fast Speed (up to 400 kHz)
● Status flags:
– Transmitter/Receiver mode flag
– End-of-Byte transmission flag
–I
2
C busy flag
● Error flags:
– Arbitration lost condition for master mode
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