Advanced-control timers (TIM1&TIM8) RM0008
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12.4.5 Status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
Bit 3 CC3IE: Capture/Compare 3 interrupt enable.
0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable.
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable.
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
Bit 0 UIE: Update interrupt enable.
0: Update interrupt disabled.
1: Update interrupt enabled.
1514131211109876543210
Reserved
CC4O
F
CC3O
F
CC2O
F
CC1O
F
Res. BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF
Res. rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0
Bit 15:13 Reserved, always read as 0.
Bit 12 CC4OF: Capture/Compare 4 Overcapture Flag.
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 Overcapture Flag.
refer to CC1OF description
Bit 10 CC2OF: Capture/Compare 2 Overcapture Flag.
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 Overcapture Flag.
This flag is set by hardware only when the corresponding channel is configured in input capture
mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
Bit 8 Reserved, always read as 0.
Bit 7 BIF: Break interrupt Flag.
This flag is set by hardware as soon as the break input goes active. It can be cleared by software if
the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
Bit 6 TIF: Trigger interrupt Flag.
This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave
mode controller is enabled in all modes but gated mode, both edges in case gated mode is
selected). It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
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