ST STM32F102 series User Manual

RM0008 Reset and clock control (RCC)
81/690
6.3.3 Clock interrupt register (RCC_CIR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved CSSC Reserved
PLL
RDYC
HSE
RDYC
HSI
RDYC
LSE
RDYC
LSI
RDYC
Res. w Res. w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
LSE
RDYIE
LSI
RDYIE
CSSF Reserved
PLL
RDYF
HSE
RDYF
HSI
RDYF
LSE
RDYF
LSI
RDYF
Res. rw rw rw rw rw r Res. r r r r r
Bits 31:24 Reserved, always read as 0.
Bit 23 CSSC Clock security system interrupt clear
Set by software to clear CSSF.
Reset by hardware when clear done.
0: CSSF not cleared
1: CSSF cleared
Bits 22:21 Reserved, always read as 0.
Bit 20 PLLRDYC PLL ready interrupt clear
Set by software to clear PLLRDYF.
Reset by hardware when clear done.
0: PLLRDYF not cleared
1: PLLRDYF cleared
Bit 19 HSERDYC HSE ready interrupt clear
Set by software to clear HSERDYF.
Reset by hardware when clear done.
0: HSERDYF not cleared
1: HSERDYF cleared
Bit 18 HSIRDYC HSI ready interrupt clear
Set by software to clear HSIRDYF.
Reset by hardware when clear done.
0: HSIRDYF not cleared
1: HSIRDYF cleared
Bit 17 LSERDYC LSE ready interrupt clear
Set by software to clear LSERDYF.
Reset by hardware when clear done.
0: LSERDYF not cleared
1: LSERDYF cleared

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English