RM0008 Serial peripheral interface (SPI)
569/690
Overrun flag (OVR)
This flag is set when data are received and the previous data have not yet been read from
SPI_DR. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE
bit is set in SPI_CR2.
In this case, the receive buffer contents are not updated with the newly received data from
the transmitter device. A read operation to the SPI_DR register returns the previous
correctly received data. All other subsequently transmitted half-words are lost.
Clearing the OVR bit is done by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register.
22.4.8 I
2
S interrupts
Table 147 provides the list of I
2
S interrupts.
22.4.9 DMA features
DMA is working in exactly the same way as for the SPI mode. There is no difference on the
I
2
S. Only the CRC feature is not available in I
2
S mode since there is no data transfer
protection system.
22.5 SPI and I
2
S registers
Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions.
22.5.1 SPI Control Register 1 (SPI_CR1) (not used in I
2
S mode)
Address offset: 0x00
Reset value: 0x0000)
Table 147. I
2
S interrupt requests
Interrupt event Event flag Enable Control bit
Transmit buffer empty flag TXE TXEIE
Receive buffer not empty flag RXNE RXNEIE
Overrun error OVR
ERRIE
Underrun error UDR
1514131211109876543210
BIDI
MODE
BIDI
OE
CRC
EN
CRC
NEXT
DFF
RX
ONLY
SSM SSI
LSB
FIRST
SPE BR [2:0] MSTR CPOL CPHA
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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