ST STM32F102 series

General-purpose timer (TIMx) RM0008
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13.4.14 Capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000
13.4.15 Capture/compare register 3 (TIMx_CCR3)
Address offset: 0x3C
Reset value: 0x0000
13.4.16 Capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000
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CCR2[15:0]
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Bits 15:0 CCR2[15:0]: Capture/Compare 2 Value.
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update
event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and
signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
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CCR3[15:0]
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Bits 15:0 CCR3[15:0]: Capture/Compare Value.
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE).
Else the preload value is copied in the active capture/compare 3 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and
signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
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CCR4[15:0]
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