ST STM32F102 series User Manual

RM0008 Controller area network (bxCAN)
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21.4.3 Reception handling
For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and guarantee data consistency, the FIFO is
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see Section 21.4.4: Identifier filtering.
Figure 198. Receive FIFO states
FIFO management
Starting from the empty state, the first valid message received is stored in the FIFO which
becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CRFR
register to the value 01b. The message is available in the FIFO output mailbox. The software
reads out the mailbox content and releases it by setting the RFOM bit in the CRFR register.
The FIFO becomes empty again. If a new valid message has been received in the
meantime, the FIFO stays in pending_1 state and the new message is available in the
output mailbox.
EMPTY
Valid Message
FMP=0x00
FOVR=0
PENDING_1
FMP=0x01
FOVR=0
Received
PENDING_2
FMP=0x10
FOVR=0
PENDING_3
FMP=0x11
FOVR=0
Valid Message
Received
Release
OVERRUN
FMP=0x11
FOVR=1
Mailbox
Release
Mailbox
Valid Message
Received
Valid Message
Received
Release
Mailbox
Release
Mailbox
Valid Message
Received
RFOM=1
RFOM=1
RFOM=1

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English