RM0008 Serial peripheral interface (SPI)
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22.5.3 SPI status register (SPI_SR)
Address offset: 08h
Reset value: 0x0002
1514131211109876543210
Reserved BSY OVR MODF
CRC
ERR
UDR
CHSID
E
TXE RXNE
Res. rrrrc_w0rrrr
Bits 15:8 Reserved. Forced to 0 by hardware.
Bit 7 BSY: Busy flag
0: SPI (or I2S) not busy
1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and reset by hardware.
Note: In master receiver-only mode (1-line bidirectional), it is forbidden to check the BSY flag.
Bit 6 OVR: Overrun flag
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to Section 22.4.7 on page 568
for the software sequence.
Bit 5 MODF: Mode fault
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to Section 22.3.8 on page 554
for the software sequence.
Note: Not used in I
2
S mode
Bit 4 CRCERR: CRC Error flag
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
Note: Not used in I
2
S mode
Bit 3 UDR: Underrun flag
0: No underrun occurred
1: Underrun occurred
This flag is set by hardware and reset by a software sequence. Refer to Section 22.4.7 on page 568
for the software sequence.
Note: Not used in SPI mode
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