Serial peripheral interface (SPI) RM0008
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22.5.7 SPI Tx CRC register (SPI_TXCRCR) (not used in I
2
S mode)
Address offset: 0x18
Reset value: 0x0000
22.5.8 SPI_I
2
S configuration register (SPI_I2SCFGR)
Address offset: 1Ch
Reset value: 0x0000
1514131211109876543210
TxCRC[15:0]
rrrrrrrrrrrrrrrr
Bits 15:0 TxCRC[15:0]: Tx CRC register
When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the
subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to
1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register.
Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF bit of
SPI_CR1 is cleared). CRC calculation is done based on CRC8.
The entire 16-bits of this register are considered when a 16-bit data frame format is selected (DFF
bit of the SPI_CR1 register is set). CRC calculation is done based on CRC16 - CCITT standard.
Note: A read to this register when the BSY flag is set could return an incorrect value.
Not used for the I
2
S mode.
1514131211109876543210
Reserved
I2SMO
D
I2SE I2SCFG
PCMS
YNC
reserv
ed
I2SSTD
CKPO
L
DATLEN
CHLE
N
rw rw rw rw rw rw rw
Bits 15:12 Reserved: Forced to 0 by hardware
Bit 11 I2SMOD: I
2
S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI or I
2
S is disabled
Bit 10 I2SE: I
2
S Enable
0: I
2
S peripheral is disabled
1: I
2
S peripheral is enabled
Note: Not used in SPI mode
Bit 9:8 I2SCFG: I
2
S configuration mode
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
Notes: This bit should be configured when the I
2
S is disabled.
Not used for the SPI mode
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