RM0008 Advanced-control timers (TIM1&TIM8)
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12.4.13 Repetition counter register (TIMx_RCR)
Address offset: 0x30
Reset value: 0x0000
12.4.14 Capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
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Reserved REP[7:0]
Res. rw rw rw rw rw rw rw rw
Bits 15:8 Reserved, always read as 0.
Bits 7:0 REP[7:0]: Repetition Counter Value.
These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from
preload to active registers) when preload registers are enable, as well as the update interrupt
generation rate, if this interrupt is enable.
Each time the REP_CNT related downcounter reaches zero, an update event is generated and it
restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition
update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition
update event.
It means in PWM mode (REP+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode.
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CCR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 CCR1[15:0]: Capture/Compare 1 Value).
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Else the preload value is copied in the active capture/compare 1 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and
signaled on OC1 output.
If channel CC1 is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
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