RM0008 General-purpose timer (TIMx)
317/690
13.4.6 Event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
Bit 2 CC2IF: Capture/Compare 2 interrupt Flag.
refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt Flag.
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some exception in
center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1
register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1
which matches the selected polarity).
Bit 0 UIF: Update interrupt flag.
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value (update if REP_CNT=0) and if the
UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to the synchro control register description), if
URS=0 and UDIS=0 in the TIMx_CR1 register.
1514131211109876543210
Reserved
TG Res. CC4G CC3G CC2G CC1G UG
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Bits 15:7 Reserved, always read as 0.
Bit 6 TG: Trigger generation.
This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0: No action.
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Bit 5 Reserved, always read as 0.
Bit 4 CC4G: Capture/compare 4 generation.
refer to CC1G description
Bit 3 CC3G: Capture/compare 3 generation.
refer to CC1G description
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