RM0008 Universal synchronous asynchronous receiver transmitter (USART)
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24.6.2 Data register (USART_DR)
Address offset: 0x04
Reset value: Undefined
24.6.3 Baud Rate Register (USART_BRR)
Note: The baud counters stop counting if the TE or RE bits are disabled respectively.
Address offset: 0x08
Reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved DR[8:0]
Res. rw rw rw rw rw rw rw rw rw
Bits 31:9 Reserved, forced by hardware to 0.
Bits 8:0 DR[8:0]: Data value.
Contains the Received or Transmitted data character, depending on whether it is read from or
written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR)
The TDR register provides the parallel interface between the internal bus and the output shift
register (see Figure 1).
The RDR register provides the parallel interface between the input shift register and the internal
bus.
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value
written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced
by the parity.
When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
DIV_Mantissa[11:0] DIV_Fraction[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, forced by hardware to 0.
Bits 15:4 DIV_Mantissa[11:0]: mantissa of USARTDIV.
These 12 bits define the mantissa of the USART Divider (USARTDIV)
Bits 3:0 DIV_Fraction[3:0]: fraction of USARTDIV.
These 4 bits define the fraction of the USART Divider (USARTDIV)
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