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ST STM32F102 series User Manual

ST STM32F102 series
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Universal synchronous asynchronous receiver transmitter (USART) RM0008
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Bit 2 NE: Noise Error Flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared by a software
sequence (an read to the USART_SR register followed by a read to the USART_DR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit which
itself generates an interrupting interrupt is generated on NE flag in case of Multi Buffer
communication if the EIE bit is set.
Bit 1 FE: Framing Error.
This bit is set by hardware when a de-synchronization, excessive noise or a break character is
detected. It is cleared by a software sequence (an read to the USART_SR register followed by a
read to the USART_DR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit which
itself generates an interrupt. If the word currently being transferred causes both frame error
and overrun error, it will be transferred and only the ORE bit will be set.
An interrupt is generated on FE flag in case of Multi Buffer communication if the EIE bit is set.
Bit 0 PE: Parity Error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by a read to the USART_DR data register). The
software must wait for the RXNE flag to be set before clearing the PE bit.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error

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ST STM32F102 series Specifications

General IconGeneral
BrandST
ModelSTM32F102 series
CategoryMicrocontrollers
LanguageEnglish

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