ST STM32F102 series

RM0008 Reset and clock control (RCC)
87/690
6.3.6 AHB Peripheral Clock enable register (RCC_AHBENR)
Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
Bit 5 TIM7RST Timer 7 reset
Set and reset by software.
0: No effect
1: Reset timer 7
Bit 4 TIM6RST Timer 6 reset
Set and reset by software.
0: No effect
1: Reset timer 6
Bit 3 TIM5RST Timer 5 reset
Set and reset by software.
0: No effect
1: Reset timer 5
Bit 2 TIM4RST Timer 4 reset
Set and reset by software.
0: No effect
1: Reset timer 4
Bit 1 TIM3RST Timer 3 reset
Set and reset by software.
0: No effect
1: Reset timer 3
Bit 0 TIM2RST Timer 2 reset
Set and reset by software.
0: No effect
1: Reset timer 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SDIO
EN
Res.
FSMC
EN
Res.
CRCE
N
Res.
FLITF
EN
Res.
SRAM
EN
DMA2
EN
DMA1
EN
Res. rw Res. rw Res. rw Res. rw Res. rw rw rw
Bits 31:11 Reserved, always read as 0.
Bit 10 SDIOEN SDIO clock enable
Set and reset by software.
0: SDIO clock disabled
1: SDIO clock enabled
Bits 9 Reserved, always read as 0.