To Next Page

To Previous Page

RM0008 Reset and clock control (RCC)

69/690

6 Reset and clock control (RCC)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx

microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the

Flash memory density ranges between 256 and 512 Kbytes.

This Section applies to the whole STM32F10xxx family, unless otherwise specified.

6.1 Reset

There are three types of reset, defined as system Reset, power Reset and backup domain

Reset.

6.1.1 System reset

A system reset sets all registers to their reset values except the reset flags in the clock

controller CSR register and the registers in the Backup domain (see Figure 4).

A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. Window Watchdog end of count condition (WWDG reset)

3. Independent Watchdog end of count condition (IWDG reset)

4. A software reset (SW reset) (see Section : Software reset)

5. Low-power management reset (see Section : Low-power management reset)

The reset source can be identified by checking the reset flags in the Control/Status register,

RCC_CSR (see Section 6.3.10: Control/status register (RCC_CSR)).

Software reset

The SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register

must be set to force a software reset on the device. Refer to the Cortex™-M3 technical

reference manual for more details.

Low-power management reset

There are two ways to generate a low-power management reset:

1. Reset generated when entering Standby mode:

This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this

case, whenever a Standby mode entry sequence is successfully executed, the device

is reset instead of entering Standby mode.

2. Reset when entering Stop mode:

This type of reset is enabled by resetting NRST_STOP bit in User Option Bytes. In this

case, whenever a Stop mode entry sequence is successfully executed, the device is

reset instead of entering Stop mode.

ST STM32F102 series User Manual

Questions and Answers: