ST STM32F102 series

RM0008 Flexible static memory controller (FSMC)
385/690
The differences with mode1 are the toggling of NADV, NOE that goes on toggling after
NADV changes and the independent read and write timings.
Table 86. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-15 0x0000
14 EXTMOD 0x1
13-10 0x0
9 WAITPOL Meaningful only if bit 15 is 1.
8 BURSTEN 0x0
7 -
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP As needed
1 MUXEN 0x0
0 MBKEN 0x1
Table 87. FSMC_TCRx bit fields
Bit No. Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x2
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) in
read. This value cannot be 0 (minimum is 1)
7-4 ADDHLD
Duration of the middle phase of the read access (ADDHLD+1 HCLK
cycles)
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) in
read.
Table 88. FSMC_BWTRx bit fields
Bit No. Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x2
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles) in
write. This value cannot be 0 (minimum is 1)
7-4 ADDHLD
Duration of the middle phase of the write access (ADDHLD+1 HCLK
cycles)
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in write.