Flexible static memory controller (FSMC) RM0008
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18.5.3 General timing rules
Signals synchronization
● All controller output signals change on the rising edge of the internal clock (HCLK)
● In synchronous write mode (PSRAM devices), the output data changes on the falling
edge of the memory clock (CLK)
18.5.4 NOR Flash/PSRAM controller timing diagrams
Asynchronous static memories (NOR Flash, SRAM)
● Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
● The FSMC always samples the data before de-asserting the chip select signal NE. This
guarantees that the memory data-hold timing constraint is met (chip enable high to
data transition, usually 0 ns min.)
● When extended mode is set, it is possible to mix modes A, B, C and D in read and write
(it is for instance possible to read in mode A and write in mode B).
Mode 1 - SRAM/CRAM
Figure 159. Mode1 read accesses
A[25:0]
NOE
(ADDSET +1) (DATAST + 1)
Memory transaction
Data strobe
NEx
D[15:0]
HCLK cycles
HCLK cycles
NWE
NBL[1:0]
data driven
by memory
ai14720c
High
2 HCLK
cycles
Data sampled
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