ST STM32F102 series User Manual

RM0008 Advanced-control timers (TIM1&TIM8)
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12.4.17 Capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000
12.4.18 Break and dead-time register (TIMx_BDTR)
Address offset: 0x44
Reset value: 0x0000
Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
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CCR4[15:0]
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Bits 15:0 CCR4[15:0]: Capture/Compare Value.
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Else the preload value is copied in the active capture/compare 4 register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and
signalled on OC4 output.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
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MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
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ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English