Inter-integrated circuit (I
2
C) interface RM0008
594/690
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I
2
C interface and the DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.
Reception using DMA
DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
Data will be loaded from the I2C_DR register to a Memory area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
channel for I
2
C reception, perform the following sequence. Here x is the channel number.
1. Set the I2C_DR register address in DMA_CPARx
register. The data will be
moved from this address to the memory after each RxNE event.
2. Set the memory address in the DMA_CMARx register. The data will be
loaded from the I2C_DR register to this memory area after each RxNE event.
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx
register. After each RxNE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx
register
5. Reset the DIR bit and configure interrupts in the DMA_CCRx register after
half transfer or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I
2
C interface and DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
23.3.8 Packet error checking
A PEC calculator has been implemented to improve the reliability of communication. The
PEC is calculated by using a programmable polynomial serially on each bit.
● PEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a
CRC-8 calculated on all message bytes including addresses and R/W bits.
– In transmission: set the PEC transfer bit in the I2C_CR1 register after the TxE
event corresponding to the last byte. The PEC will be transferred after the last
transmitted byte.
– In reception: set the PEC bit in the I2C_CR1 register after the RxNE event
corresponding to the last byte so that the receiver sends a NACK if the next
received byte is not equal to the internally calculated PEC. In case of Master-
Receiver, a NACK must follow the PEC whatever the check result.
● A PECERR error flag/interrupt is also available in the I2C_SR1 register.
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