RM0008 Debug support (DBG)
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Refer to the Cortex-M3 r1p1 TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.
The ACK Response must be followed by a turnaround time only if it is a READ transaction or
if a WAIT or FAULT acknowledge has been received.
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
26.8.3 SW-DP state machine (Reset, idle states, ID code)
The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default ARM one and is set at
0x1BA01477 (corresponding to Cortex-M3 r1p1).
Table 162. Packet request (8-bits)
Bit Name Description
0 Start Must be “1”
1 APnDP
0: DP Access
1: AP Access
2RnW
0: Write Request
1: Read Request
4:3 A(3:2) Address field of the DP or AP registers (refer to Table 161)
5 Parity Single bit parity of preceding bits
6Stop 0
7Park
Not driven by the host. Must be read as “1” by the target
because of the pull-up
Table 163. ACK response (3 bits)
Bit Name Description
0..2
ACK
001: FAULT
010: WAIT
100: OK
Table 164. DATA transfer (33 bits)
Bit Name Description
0..31
WDATA or
RDATA
Write or Read data
32
Parity
Single parity of the 32 data bits
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