ST STM32F102 series

CRC calculation unit RM0008
46/690
3.4.2 Independent Data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
3.4.3 Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved
IDR[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved
Bits 7:0 General-purpose 8-bit data register bits
Can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved
RESET
w
Bits 31:1 Reserved
Bit 0
RESET bit
Resets the CRC calculation unit and sets the data register to FFFF FFFFh.
This bit can only be set, it is automatically cleared by hardware.