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ST STM32F102 series User Manual

ST STM32F102 series
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Debug support (DBG) RM0008
656/690
JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only
the SWCLK and SWDIO pins.
This sequence is:
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted
first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1
26.4 Pinout and debug port pins
The STM32F10xxx MCU is available in various packages with different numbers of available
pins. As a result, some functionality related to pin availability may differ between packages.
26.4.1 SWJ debug port pins
Five pins are used as outputs from the STM32F10xxx for the SWJ-DP as alternate functions
of General Purpose I/Os. These pins are available on all packages.
26.4.2 Flexible SWJ-DP pin assignment
After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements the REMAP_DBGAFR register to disable
some part or all of the SWJ-DP port and so releases the associated pins for General
Purpose I/Os usage. This register is mapped on an APB bridge connected to the Cortex-M3
System Bus. Programming of this register is done by the user software program and not the
debugger host.
Table 158. SWJ debug port pins
SWJ-DP pin name
JTAG debug port SW debug port Pin
assign
ment
Type Description Type Debug assignment
JTMS/SWDIO I
JTAG Test Mode
Selection
I/O
Serial Wire Data
Input/Output
PA13
JTCK/SWCLK I JTAG Test Clock I Serial Wire Clock PA14
JTDI I JTAG Test Data Input - - PA15
JTDO/TRACESWO O JTAG Test Data Output -
TRACESWO if async trace
is enabled
PB3
JNTRST I JTAG Test nReset - - PB4

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ST STM32F102 series Specifications

General IconGeneral
BrandST
ModelSTM32F102 series
CategoryMicrocontrollers
LanguageEnglish

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