Flexible static memory controller (FSMC) RM0008
380/690
Figure 165. ModeB write accesses
The differences with mode1 are the toggling of NADV and the independent read and write
timings when extended mode is set (Mode B).
Table 80. FSMC_BCRx bit fields
Bit
number
Bit name Value to set
31-15 0x0000
14 EXTMOD 0x1 for mode B, 0x0 for mode 2
13-10 0x0
9 WAITPOL Meaningful only if bit 15 is 1.
8 BURSTEN 0x0
7 -
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP 10 (NOR Flash).
1 MUXEN 0x0
0 MBKEN 0x1
A[25:0]
NOE
(ADDSET +1) (DATAST + 1)
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven by FSMC
ai15110b
1HCLK
To Next Page
Loading...
Need help?
General
