RM0008 Revision history
683/690
08-Feb-2008 3
Figure 4: Power supply overview on page 48 modified.
Section 6.1.2: Power reset on page 70 modified.
Section 6.2: Clocks on page 70 modified.
Definition of Bits 26:24 modified in Section 7.4.2: AF remap and debug I/O
configuration register (AFIO_MAPR) on page 117.
AFIO_EVCR bits corrected in Table 35: AFIO register map and reset values on
page 122.
Number of maskable interrupt channels modified in Section 8.1: Nested
vectored interrupt controller (NVIC) on page 123
.
Section 9.3.5: Interrupts on page 138 added. Small text changes.
Examples modified in Figure 86: 6-step generation, COM example
(OSSR=1) on page 236.
Table 55: Output control bits for complementary OCx and OCxN channels
with break feature on page 263 modified.
Register names modified in Section 21.6.4: CAN filter registers on
page 534.
Small text change in Section 23.3.3: I2C master mode on page 586.
Bits 5:0 frequency description modified in Section 23.6.2: Control register 2
(I2C_CR2) on page 599.
Section 20.3.1: Description of USB blocks on page 470 modified.
Section 22.3.4: Simplex communication on page 551 modified.
Section 22.3.6: CRC calculation on page 552 modified.
Note added in BUSY flag on page 552.
Section 22.3.9: Disabling the SPI on page 555 added.
Appendix A: Important notes, removed.
22-May-2008
4
continued
on next
page
Reference manual updated to apply to devices containing up to 512 Kbytes
of Flash memory (High-density devices). Document restructured. Small text
changes. Definitions of Medium-density and High-density devices added to
all sections.
In Section 2: Memory and bus architecture on page 33:
– Figure 1: System architecture on page 33, Figure 2: Memory map on
page 35, Table 1: Register boundary addresses on page 36 updated
– Note and text added to AHB/APB bridges (APB) on page 34
– SRAM size in Section 2.3.2: Embedded SRAM on page 38
– Section 2.3.4: Embedded Flash memory on page 39 updated (Flash size,
page size, number of pages, Reading Flash memory, Ta bl e 4 : F la s h
module organization (High-density devices) on page 41 added)
– Prefetch buffer on/off specified in Reading Flash memory
bit_number definition modified in Section 2.3.3: Bit banding on page 38.
Section 3: CRC calculation unit on page 44 added (Table 1: Register
boundary addresses on page 36 updated, Figure 2: Memory map on
page 35 updated and CRCEN bit added to Section 6.3.6: AHB Peripheral
Clock enable register (RCC_AHBENR) on page 87).
Entering Stop mode on page 54 specified.
Updated in Section 5: Backup registers (BKP) on page 61: number of
backup registers and available storage size and Section 5.1: BKP
introduction. ASOE definition modified in Section 5.4.2: RTC clock
calibration register (BKP_RTCCR) on page 63.
Table 174. Document revision history (continued)
Date Revision Changes
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