ST STM32F102 series - ADC Injected Data Register X (Adc_Jdrx) (X= 1; ADC Regular Data Register (ADC_DR)

RM0008 Analog-to-digital converter (ADC)
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10.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
10.12.14 ADC regular data register (ADC_DR)
Address offset: 0x4C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA[15:0]
rrrrrrr r r r r r r r r r
Bits 31:16 Reserved, must be kept cleared.
Bits 15:0 JDATA[15:0]: Injected data
These bits are read only. They contain the conversion result from injected channel x. The data is left
or right-aligned as shown in Figure 26 and Figure 27.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC2DATA[15:0]
rrrrrrr r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[15:0]
rrrrrrr r r r r r r r r r
Bits 31:16 ADC2DATA[15:0]: ADC2 data
– In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to Section 10.9: Dual
ADC mode
– In ADC2 and ADC3: these bits are not used
Bits 15:0 DATA[15:0]: Regular data
These bits are read only. They contain the conversion result from the regular channels. The data is
left or right-aligned as shown in Figure 26 and Figure 27.