Revision history RM0008
680/690
27 Revision history
Table 174. Document revision history
Date Revision Changes
19-Oct-2007 1
Document reference number changed from UM0306 to RM008. The
changes below were made with reference to revision 1 of 01-Jun-2007 of
UM0306.
EXTSEL[2:0] and JEXTSEL[2:0] removed from Table 42: ADC pins on
page 151 and V
REF+
range modified in Remarks column.
Notes added to Section 10.3.9 on page 154, Section 10.9.2 on page 162,
Section 10.9.7 on page 165 and Section 10.9.9 on page 166.
SPI_CR2 corrected to SPI_CR1 in 1 clock and 1 bidirectional data wire on
page 551.
f
CPU
frequency changed to f
PCLK
in Section 22.2: SPI and I
2
S main features
on page 544.
Section 22.3.6: CRC calculation on page 552 and Section 22.3.7: SPI
communication using DMA (direct memory addressing) on page 553
modified.
Note added to bit 13 description changed in Section 22.5.1: SPI Control
Register 1 (SPI_CR1) (not used in I
2
S mode) on page 569. Note for bit 4
modified in Section 22.5.3: SPI status register (SPI_SR) on page 573.
On 64-pin packages on page 49 modified.
Section 7.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 on
page 110 updated.
Description of SRAM at address 0x4000 6000 modified in Figure 2: Memory
map on page 35 and Table 1: Register boundary addresses.
Note added to Section 20.2: USB main features on page 468 and
Section 21.2: bxCAN main features on page 499.
Figure 4: Power supply overview and On 100-pin and 144- pin packages
modified.
Formula added to Bits 25:24 description in CAN bit timing register
(CAN_BTR) on page 527.
Section 9.3: DMA functional description on page 135 modified.
Example of configuration on page 670 modified.
MODEx[1:0] bit definitions corrected in Section 7.2.2: Port configuration
register high (GPIOx_CRH) (x=A..G) on page 106.
Downcounting mode on page 213 modified.
Figure 76: Output stage of capture/compare channel (channel 4) on
page 224 and Figure 78: Output compare mode, toggle on OC1. modified.
OCx output enable conditions modified in Section 12.3.10: PWM mode on
page 228.
Section 12.3.19: TIMx and external trigger synchronization on page 243 title
changed.
CC1S, CC2S, CC3S and CC4S definitions modified for (1, 1) bit setting
modified in Section 12.4.7: Capture/compare mode register 1
(TIMx_CCMR1) and Section 12.4.8: Capture/compare mode register 2
(TIMx_CCMR2).
CC1S, CC2S, CC3S and CC4S definitions for (1, 1) bit setting modified in
Section 13.4.7: Capture/compare mode register 1 (TIMx_CCMR1) and
Section 13.4.8: Capture/compare mode register 2 (TIMx_CCMR2).
AFIO_EVCR pins modified in Table 35: AFIO register map and reset values
on page 122. Section 12.3.6: Input capture mode on page 224 modified.
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