Serial peripheral interface (SPI) RM0008
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22.5.9 SPI_I
2
S Prescaler register (SPI_I2SPR)
Address offset: 20h
Reset value: 0000 0010 (0002h)
1514131211109876543210
Reserved
MCKO
E
ODD I2SDIV
Res. rw rw rw
Bits 15:10 Reserved: Forced to 0 by hardware
Bit 9 MCKOE: Master Clock Output Enable
0: Master clock output is disabled
1: Master clock output is enabled
Notes: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in
master mode.
Not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 22.4.3 on page 564
Notes: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in
master mode.
Not used in SPI mode
Bit 7:0 I2SDIV: I
2
S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 22.4.3 on page 564
Notes: These bits should be configured when the I
2
S is disabled. It is used only when the I
2
S is in
master mode.
Not used in SPI mode.
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