RM0008 Basic timer (TIM6&7)
335/690
Figure 148. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded)
Figure 149. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
14.3.3 Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 150 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 0732 33 34 35 3631
Auto-reload register
FF 36
Write a new value in TIMx_ARR
CK_INT
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 07F1 F2 F3 F4 F5F0
Auto-reload preload register
F5 36
Auto-reload shadow register
F5 36
Write a new value in TIMx_ARR
CK_PSC
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